[update: added photo of top side, since the ware was already guessed – just for more enjoyment]
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Can we talk about that PCB tho. Is that ENIG? Whats the deal with all those pads all over the place? Some might even look like probe points for testing before assembly, but majority are just random ground on upper pour. WTF is this? Flex because they got a deal on cheap ENIG finish (useless in this product)?
FNIRSI do love them some Shanzhai
1013D advertised 100MHz BW, measured 30MHz
1014D same analog BW scam as above, plus “1GSa/s” scope build with dual 100MHz AD9288 per channel
HRM-10 ESR tester giving random readings
DSO-TC3 giving same random ESR readings, not able to tell transistors apart
DPS-150 reports of negative voltage when OFF
It all feels like students final year projects turned into products with no supervision.
I feel like I’ve see this particular design quirk on ground pours before but I don’t know the reason.
In the case that the trace or plane is tinned to improve current carrying capacity, I found a reference stating “Tinning a large single area of copper is difficult and will lead to an uneven thickness of solder over the copper area. By breaking down the area into individual unmasked “tracks” the tinning process works much better.” https://social.afront.org/@stylus/113773048962878798
However, in this case there is no extra tin on the pads…
Ah yes I know what you’re referring to in this one – this is when they take the PCB and run it through a wave solder bath to make an extra thick plating of solder to effectively increase the ampacity of traces. True that if you make a big wide copper area, what you end up with is a big ball of tin on the side of the trace dictated by gravity as the thing is cooling – by dividing a large trace into smaller areas where surface tension dominates you can keep droplets rounder and thus have more cross-sectional area for conduction.
However in this case, one thing that’s missing from the photo is that where those gold holes are – there is a massive thermal gap pad. Like, no joke, a 1cm thick piece of gap filler material.
Almost certainly the purpose in this case is to remove soldermask so that the gap pad can contact the copper directly, without the soldermask layer serving as an insulator in between. Even the tiniest layer of insulator can kill thermal performance in these situations (hence why we use heat sink grease/gap pads in the first place to ensure good contact to heat sinks). Most likely they didn’t pull back *all* the soldermask to save on ENIG costs and maybe also to improve yield as it’s hard to get large regions of defect free ENIG (don’t know why – just something I’ve observed doing touch surfaces with ENIG).
Given the heat sinking, I’m guessing they can’t sustain their rated power of 150W. Like, sure, for a short test it’ll provide the amps but likely to overheat after a few minutes. Forced air over the supply would probably help, or mounting it to an aluminum base maybe. Fortunately I don’t need to run this anywhere near that limit – it’s perfect for a cheap drop-in battery simulator that also plots a graph of amperage over time.
Added the top side photo since the ware was guessed so quickly – kind of surprised but also not surprised that this was so instantly recognized.
The thermal pad mounts on top of the area designated by the large square outline in the silkscreen on the original image, fwiw. So it doesn’t fully cover all the openings in the soldermask but it overlaps many of them (perhaps they were experimenting with various sizes of pad – the gap pad is pretty expensive material).
The extended lead openings on the FETs makes me also think that the soldermask pull back is for thermal performance, because there’s no way you’d put this through a wave solder machine to tin the openings – it’d just end up shorting out those leads. But one of the best ways to cool a die is through its leads, and getting a gap pad in direct contact with the copper soldered onto the pins is consistent with that notion.
I’m actually sort of impressed at the mount of UI they do with that little 48-lead QFP microcontroller. I guess looks can be deceiving, you can stick a lot of transistors in something that size these days – but it’s probably got some decent FLASH capacity to hold the graphics libraries, fonts, etc.
V+/V-, black solder mask, shaved off labels — FNIRSI DPS-150?
That looks exactly like what it would be. Well done!!!
Hole in one, nice.
Can we talk about that PCB tho. Is that ENIG? Whats the deal with all those pads all over the place? Some might even look like probe points for testing before assembly, but majority are just random ground on upper pour. WTF is this? Flex because they got a deal on cheap ENIG finish (useless in this product)?
FNIRSI do love them some Shanzhai
1013D advertised 100MHz BW, measured 30MHz
1014D same analog BW scam as above, plus “1GSa/s” scope build with dual 100MHz AD9288 per channel
HRM-10 ESR tester giving random readings
DSO-TC3 giving same random ESR readings, not able to tell transistors apart
DPS-150 reports of negative voltage when OFF
It all feels like students final year projects turned into products with no supervision.
I feel like I’ve see this particular design quirk on ground pours before but I don’t know the reason.
In the case that the trace or plane is tinned to improve current carrying capacity, I found a reference stating “Tinning a large single area of copper is difficult and will lead to an uneven thickness of solder over the copper area. By breaking down the area into individual unmasked “tracks” the tinning process works much better.”
https://social.afront.org/@stylus/113773048962878798
However, in this case there is no extra tin on the pads…
Ah yes I know what you’re referring to in this one – this is when they take the PCB and run it through a wave solder bath to make an extra thick plating of solder to effectively increase the ampacity of traces. True that if you make a big wide copper area, what you end up with is a big ball of tin on the side of the trace dictated by gravity as the thing is cooling – by dividing a large trace into smaller areas where surface tension dominates you can keep droplets rounder and thus have more cross-sectional area for conduction.
However in this case, one thing that’s missing from the photo is that where those gold holes are – there is a massive thermal gap pad. Like, no joke, a 1cm thick piece of gap filler material.
Almost certainly the purpose in this case is to remove soldermask so that the gap pad can contact the copper directly, without the soldermask layer serving as an insulator in between. Even the tiniest layer of insulator can kill thermal performance in these situations (hence why we use heat sink grease/gap pads in the first place to ensure good contact to heat sinks). Most likely they didn’t pull back *all* the soldermask to save on ENIG costs and maybe also to improve yield as it’s hard to get large regions of defect free ENIG (don’t know why – just something I’ve observed doing touch surfaces with ENIG).
Given the heat sinking, I’m guessing they can’t sustain their rated power of 150W. Like, sure, for a short test it’ll provide the amps but likely to overheat after a few minutes. Forced air over the supply would probably help, or mounting it to an aluminum base maybe. Fortunately I don’t need to run this anywhere near that limit – it’s perfect for a cheap drop-in battery simulator that also plots a graph of amperage over time.
Added the top side photo since the ware was guessed so quickly – kind of surprised but also not surprised that this was so instantly recognized.
The thermal pad mounts on top of the area designated by the large square outline in the silkscreen on the original image, fwiw. So it doesn’t fully cover all the openings in the soldermask but it overlaps many of them (perhaps they were experimenting with various sizes of pad – the gap pad is pretty expensive material).
The extended lead openings on the FETs makes me also think that the soldermask pull back is for thermal performance, because there’s no way you’d put this through a wave solder machine to tin the openings – it’d just end up shorting out those leads. But one of the best ways to cool a die is through its leads, and getting a gap pad in direct contact with the copper soldered onto the pins is consistent with that notion.
I’m actually sort of impressed at the mount of UI they do with that little 48-lead QFP microcontroller. I guess looks can be deceiving, you can stick a lot of transistors in something that size these days – but it’s probably got some decent FLASH capacity to hold the graphics libraries, fonts, etc.
They really cranked the lazer up to remove the chip marking. ;) Just a little more and you can see the bond wires. LOL