The Ware for July 2026 is shown below.
I’ve got silicon on the brain, so I’m going to give a die shot another go at name that ware. Hopefully this one is a bit easier than the last one. This excerpt is a design pattern I look for and find on almost every SoC. It’s technically showing a bit more than just the part I’m focused on, so as a hint I’m primarily interested in identifying the structure towards the lower left corner of this image.
If you’ve seen one of these before, you’ll know what it is – it’s pretty unmistakable, and a design pattern that’s highly conserved across processes, nodes and foundries. Bonus points to anyone that can explain some of the reasons why things are organized the way they are!
Is it a io matrix? To remap the internal iic, adc, gpio and so on to whatever pin you want?
I assume you mean the 10×10 and 3×3 square structures? They look like large transistors. Given they’re not around the periphery, they’re not I/O pads. so, they’re probably part of LDO circuits to help generate all the silly voltages a modern SoC needs. The different sizes of the arrays are probably due to the expected current draw on them. Putting them on the periphery is probably a good idea thermally and for supply reasons.
They count as I/O as they probably need at least a power in pad, a ground pad, and maybe a bypass cap pad. They’re also power ingress, so it makes sense to keep them near the periphery. From a thermal point, you want to keep the power dissipation of the chip well distributed–the logic (CPUs, etc) need to be all next to each other, so they fight for the power budget in the middle of the chip. So, something like this that can easily be moved to the periphery is probalby a good thing to move away.
I don’t expect they need to be square grids, but it’s probably the easies to do with a design tool. That also probably explains why they are arrays of similarly sized transistors–each one is probably as big as the process is spec’ed for. Anything different (larger) would need to be custom and these are probably generated by a tool that’s told how much current it’s going to need to source, so it just puts in N parts and if N is a square, so much the better.
Conductive layer grids? Perhaps a shield to prevent tampering or readout from a particular section of PROM.
They don’t look like tamper detect lines (those would be one long zigzag, so a cut at any point cuts the whole trace).
The waffle texture is why it’s called a wafer.
that’s a good one
Die shots are definitely tricky, I found it really helpful to focus on the specific area of the silicon during the process.
I’m guessing that it is power related since it is on the edge/corner of the die where most input power & ground pad(s) will be located.
My first guess would be capacitors (second would be for power transistors) for the the power regulator. Certainly the most optimized layout to keep connections between them really close.
They are test/alignment structures for QC purposes.