main:				
	ALLOCATEC 0x4, q0	;  memory latency test
	MMS       q1, q2        ;  store some data
	MML       q8, q9        ;  setup load
	MOVE      @q0, q8
	MOVE      @q0, q1       ;  setup store
	MOVECL    4, q3
	MOVECL    1, q4
	MOVE      q4, q1
	MOVE      q3, q2
	MOVECL    8, q5
wait:
	SUBC      @q5, 1, @q5    ;  wait for store to occur
	SEQC      @q5, 0, q6
	BRZ       q6, wait
	MOVECL    1, q4
	MOVE      q4, q8        ; request data here
	MOVE      q9, q10       ; latency to response is time till this unblocks
	PRINTQX   q10
	HALT
