Introducing lowRISC

There’s a new, open-to-the-RTL CPU project called lowRISC.

lowRISC is producing fully open hardware systems. From the processor core to the development board, our goal is to create a completely open computing eco-system.

Our open-source SoC (System-on-a-Chip) designs will be based on the 64-bit RISC-V instruction set architecture. Volume silicon manufacture is planned as is a low-cost development board.

lowRISC is a not-for-profit organisation working closely with the University of Cambridge and the open-source community.

This is a positive development for the open source hardware community and I’m excited and honored to be included on their technical advisory board. Can’t wait to play with it!

5 Responses to “Introducing lowRISC”

  1. Adam says:

    Very exciting project! Will be cool to follow the development of this.

  2. I’m kind of in two minds here, I’ve seen a lot of people go down this route and no one succeed in making a viable result.

    Looking at RISCV I’m a bit worried that there’s only a user space spec – not even a spec of what an exception does – I understand why that exists but to build an ecosystem you need a unified kernel (look at the mess that the linux ARM kernel has become with so many interrupt controllers/etc) you need a common hardware spec for programmers

    I’ve built CPUs in the past and know that getting exceptions, interrupts, traps, the tiny details and differences right is actually really really hard, and so important – if you’re planning a whole architecture up front you want to get this right … from the beginning – how are you going to handle multiple cores? (both hyperthreaded and real ones, and NUMA) – how are interrupts distributed to CPUs? TLBs shot down? how about dealing with sharing with DMA engines (and TLBs) especially graphics – building a phone how do you keep the radio code in it’s own little NSA proof box.

    You get the idea, please don’t leave this stuff up to the implementor, instead do a general multi-core spec, and a SoC subset

    • Chris says:

      The RISC-V supervisor spec exists but has not been publicly released yet. Silicon implementations exist that are both multi-core and running Linux. You’re right though – all of the stuff you mentioned is very hard and very important.

  3. Taylor says:

    I was wondering how it was related to OpenRISC (Julius Baxter from OpenRISC is involved). The user-level ISA spec says:
    We are far from the first to contemplate an open ISA design suitable for hardware implementation. We also considered other existing open ISA designs, of which the closest to our goals was the OpenRISC architecture. We decided against adopting the OpenRISC ISA for several technical reasons:
    • OpenRISC has condition codes and branch delay slots, which complicate higher performance implementations.
    • OpenRISC uses a fixed 32-bit encoding and 16-bit immediates, which precludes a denser instruction encoding and limits space for later expansion of the ISA.
    • OpenRISC does not support the 2008 revision to the IEEE 754 floating-point standard.
    • The OpenRISC 64-bit design had not been completed when we began.

    (There’s also LatticeMico32, which is free but 32-bit-only; and LEON and OpenSPARC, both of which are free SPARC implementations.)

  4. andrea says:

    i hope it’s not too OT.

    another interesting open source project recently started is this GplGPU.

    https://github.com/asicguy/gplgpu
    http://gplgpu.com/?p=88

    it’s said it comes from a late nineties industrial product gone out of business. maybe can be revived and run on Novena SP6LX45

    interesting times we live in..

Leave a Reply