45 nm High-K Transistors

I just noticed that Intel announced Hi-K dielectric transistors at the 45 nm node. It’s interesting that they are using a metal gate along with a deposited Hafnium-based dielectric…ironically, we’ve returned full-circle to the “metal-oxide-semiconductor” transistor structure (for decades it’s actually been “(salicided) polysilicon-oxide-semiconductor” devices, not quite true to the original acronym of MOS). It will be interesting to see how they solve the self-alignment issues associated with not using a native oxide grown on the silicon. The tear-down of these devices will be one Chipworks report worth buying. Or I suppose I could just wait a couple of extra months until the reversers are done and more papers/patents are published. I noticed that Intel made a point of saying that their Hafnium compound is a trade secret, which probably means that even once the guys have determined the atomic structure and stoichiometry of the gate using techniques like EDS, there is some extra secret sauce in how the compounds are piped into the deposition chamber and so forth that Intel isn’t even going to patent, and instead [attempt to] protect like the secret formula for Coca-Cola.

Also, the even more interesting question for me is if this technology can be extended to substrates such as GaAs or InP. III-V devices can’t grow a good native oxide and have lagged behind Silicon as the preferred material for manufacturing because of this problem. Now, Silicon has metal gates and a non-native oxide at the 45 nm node…

The mind boggles. If you could port this technology to InP–assuming you could start growing larger wafers (or perhaps even not? at 45 nm you can pack a lot of circuits on a 2″ or 4″ wafer)–you could start talking about some very interesting integrated optical systems, not to mention some wicked fast processors and even better performance RF devices.

12 Responses to “45 nm High-K Transistors”

  1. pt says:

    hardocore, this might be the best blog post in the history of blog posts.

  2. DCFluX says:

    I never had a problem using CMOS chips. They say to take all these cautions or you may blow them up with static. I have never seen a CMOS chip go bad. As a mater of fact the only chips I have seen routinely blow up have been the NE555 series, which you won’t know until you go to touch one.

    Didn’t someone say there is a limit to how small they are going to be able to get down to? I think it was 5nm, supposedly any smaller and the electrons will jump the tracks whether they are gated or not.

  3. Karin says:

    Yay for accurate acronyms. POSFET sounds kind of obscene, anyway.

    Interesting development…thanks for the heads-up. Miss ya.

  4. Kriss says:

    It would be possible and interesting to see a high gate count super fast GaAs CPU. I would expect a really good light show from the device too. If I remember correctly*, large GaAs wafers are hard to make because at large wafer sizes of 3 to 4″, the wafer is too brittle. The Hafnium looks pretty good on heat resistance. ( http://en.wikipedia.org/wiki/Hafnium ) I guess everyone will be speculating on what they mix with the Hafnium to get the hexagon atomic structure to stay on Si’s cubic.

  5. Robert says:

    There were some suggestive paper titles at the last IEDM – the answer may be implicit in one of those.

    One of the interesting device types in III-N is MISHFETs, where a gate oxide is added onto a HEMT. I wonder if hafnia might adapt to something like that with SiGe heterostructures?

    And the bad news in process development this week was that TI is exiting advanced process development – I’m stunned.

  6. bunnie says:

    Nice to see you drop by Karin :)

    I was pondering this some more the other day and I’m wondering if the Hafnium based compound is crystalline or amorphous. SiO2 is amorphous, but if the Hi-K dielectric is crystalline then the exact composition and process could rely on the lattice constant and specific surface chemistry of the silicon substrate for uniform growth. On the other hand, I have heard that people have been able to grow thin films of lattice-matched strained III-V compounds on silicon. Maybe you could build a shallow channel out of strained III-V on an Si substrate and then cap it with the metal gate. Well, there are a lot of factors I’m neglecting here…I don’t know the bandgaps of these materials well enough to recall if you could make a PHEMT out of this structure, for example…

  7. Randy says:


    I’ve seen more than a few devices die of ESD. Putting the nerd(ier) glasses on, my ESD training materials said that static failures don’t necessarily show up immediately – due to metal migration, they can fail days / months / years down the road. Of course, the ones that fail immediately make for some nice pictures of the affected input cell :)

    Those, of course, aren’t the interesting ones. A more interesting one was when someone hit a chip with cold spray directly to do a temperature test, causing an immediate contact fault – it would only work when touched from then on. The given solution of “we can only ship 10 of them, I guess” didn’t go over well with the tester.

    Another time, out of sheer frustration, a friend and I managed to set the Code Protection fuse on a PIC16F628A – permanently – using only a wall 10 feet away from the person throwing said chip.

    And never forget that while any diode can emit light once, no diode can emit epoxy more than once. But that’s just entertaining.

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