This board is from my personal collection of “favorite boards” that I’ve collected over the years. A lot of old memories associated this one – both figuratively and literally.
I’ve received some feedback that gmail in particular is marking my email updates as spam. Not sure I have a good way to fix this yet, as the blog is also under heavy attack from automated AI spammers at the same time (to the tune of several thousand requests a day).
You’ll notice that the blog has no ads, so I also have no budget for moderation, paid mailers, or fancy anti-spam tools. I’ll noodle on a durable solution to this problem in my copious spare time, but for now, if you’re not receiving the email updates, please try to convince Google this is not spam by marking it as ham in your inbox. Yes, have also received feedback that this is ineffective and that “the way” is to pay a service that specializes in sending spam *ahem* marketing emails, but see my previous comment about this being a lean, ad-free blog. But, maybe if enough readers mark the emails as not spam, “The Algorithm” might be convinced people actually wanted the updates they signed up for?
The Ware for May 2026 is, in FETguy’s words: “one of many large pc boards of a Rodgers Instrument Co church organ. The core memory was used to store and recall settings of the organ’s “stops”. There were 5 core memory boards in this instrument which differ in how many words were implemented. I photographed the largest one, which has 19 x 10 bit words, of which one is a spare, and then another word, I guess also spare, with no corresponding drive circuitry populated. So, 200 cores of which 180 were actually used.”
Here’s the unredacted version of the ware – includes a patent number which has more details about how it works. I love the design-for-repair, self-documenting nature of this board!
Nobody quite guessed the true nature of the ware, so this month there’s just a solution and no prize.
This month’s ware is on a theme similar to last month’s but about…50 years older. Lots of things change over the years, but the geometric organization of an array never goes out of style. On the other hand, I increasingly miss things that were designed for repair, containing self-documenting features like this one.
Huge thanks again to FETguy and Renew Computers in San Rafael, CA for contributing this gem!
Seems like I overestimated people’s interest in looking at silicon images! Congrats to k8 for attempting the challenge, I appreciate the participation. email me for your prize!
Recall that the list of possible memory dimensions is limited to a list of 28 possible types of memories. Given that, here’s the mapping of macros to memory types:
Macro A – bioram1kx32 single port
Macro B – udcmem1088x64 dual port
Macro C – rf512x32 single port
Macro D – rdram1kx32 dual port
Macro E – aoram1kx36 single port (high density)
Macro F – udcmem256x64 dual port
Macro G – ifram32kx36 single port (high density)
In addition to naming the winner and the solution, stay tuned for a follow-up post walking through how to read the macros, and why I thought it would be interesting / important to try.
The Ware for April 2026 is a little bit different. Instead of showing a circuit board, I thought it’d be interesting to go inside the chips themselves and try to identify what’s happening on at the silicon level.
Since chip reading isn’t a widely spread skill, we’ll start with a gentle introduction. For this series of wares, I’ll tell you exactly which chip these images are from: they’re from the Baochip-1x. It’s unique in that at least some of the source code is available – enough of it to give significant hints as to what’s going on. It’s also unique in that it was packaged to explicitly facilitate non-destructive IR imaging, thus allowing us to look at the chip without destroying it.
A good place to start for chip reading is learning how to read RAM macros. So, this month’s ware consists of several RAM macros. The challenge is to guess the total number of bits (given as an X by Y amount) in each example. Each of these RAMs exist inside the Baochip-1x, so that pre-constrains the space of valid guesses. Here’s another hint: it’s typical for all RAM to be wired into a “built in self test” (BIST) system. Such a system would effectively contain a central index of all RAM sizes.
SRAM architecture itself hasn’t changed much over the years. I pulled my copy of “Principles of CMOS VLSI Design” (2nd edition) from 1993 off the bookshelf and checked – at a high level, these macros still reflect exactly what’s taught in that book If you don’t have a copy of that book, there’s some pretty good modern resources on the internet that offer an overview of the basic structure of SRAM macros.
All of the macros show above are at the exact same resolution except for “Macro G” – you’ll need to click on that file to download a version that’s at full size (it’s a 2MiB PNG). Also note that the macros are not “tight cropped” – I left some of the standard cells as context around the macros. Those cells are not part of the competition this month, but I like to leave them in because it helps to have the cells in-frame to get a sense of scale.
These images are courtesy of Fail Sec Labs, and done with a Hamamatsu iPhemos-MP 1.3um LSM. This is a non-destructive infra-red imaging technique similar to IRIS, but done using a very expensive machine equipped with a laser and precision mechano-optics, and thus capable of achieving a higher resolution than IRIS. A homebrew IRIS is able to resolve many of the details visible in these images, but not with the clarity and contrast of the iPhemos-MP system. Also note that the images presented here are picked from the raw, unstitched data, and hand-stitched to reduce artifacts.
If you’d like to compare and contrast the various techniques, here’s the full-chip image files taken by various systems for download:
